Nvidia Announces New Rubin CPX Chip for Complex AI Tasks

Nvidia Corporation has introduced a new product, Rubin CPX, designed to improve the efficiency of complex artificial intelligence tasks such as video generation and software development.

Nvidia Announces New Rubin CPX Chip for Complex AI Tasks

Nvidia, a key player in the artificial intelligence computing market, has announced a new product designed to tackle complex tasks such as video generation and software development.

The new product, called Rubin CPX, is scheduled for release in late 2026. It will be available as boards that can be integrated into existing servers or used as standalone systems inside data centers.

The company says the development builds on its new Rubin product line and is aimed at improving the efficiency of certain types of AI computing. This reflects Nvidia's rapid pace of hardware and software innovation, which allows it to maintain its market leadership.

Nvidia explains that some steps in the AI ​​inference process, where the system generates responses to queries, are not yet efficient enough. In the current architecture, a single GPU processes incoming data, generates and delivers a response. The new architecture splits the steps of understanding a query and generating a response across different types of GPUs, which the company claims will make the hardware more efficient.

The new systems, which cost $100 million to develop, could potentially generate $5 billion in revenue for Nvidia customers. It’s part of the company’s strategy to demonstrate a return on investment in expensive AI hardware. Analysts estimate that Nvidia’s data center unit will generate $184 billion in revenue this fiscal year.

CEO Jensen Huang said CPX is the first chip purpose-built for AI models that operate on massive amounts of data, called tokens.

In the area of ​​code generation, systems based on the new chip are expected to be able to work not on individual fragments, but on large-scale software projects. In terms of video, the new solution will be able to perform decoding, encoding and data processing on a single chip.

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